Genetic algorithms in floorplan design of VLSI circuits | |
| Author | Dey, Abhijit |
| Call Number | AIT Thesis no. CS-93-04 |
| Subject(s) | Integrated circuits--Very large scale integration Genetic algorithms Architecture, Domestic--Designs and plans |
| Note | A thesis submitted in partial fulfillment of the requirement for the degree of the Master of Engineering |
| Publisher | Asian Institute of Technology |
| Abstract | Floorplanning of VLSI circuits is a complex combinatorial problem which is shown to be NP complete. We have applied Genetic Algorithms using polish expression as chromosomal representation instead of binary representation for solving floorplan design. We have experimented by extending Genetic Algorithms by varying mutation probability, crossover probability and wirelength coefficient using a fixed schedule as suggested by some researchers. We have also experimented by exponentially varying mutation probability over the generations. We have compared our experimental results with those published. |
| Year | 1993 |
| Type | Thesis |
| School | School of Engineering and Technology |
| Department | Department of Information and Communications Technologies (DICT) |
| Academic Program/FoS | Computer Science (CS) |
| Chairperson(s) | Sadananda, Ramakoti; |
| Examination Committee(s) | Kanchana Kanchanasut;Batanov, Dentcho N.; |
| Scholarship Donor(s) | Government of Finland; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 1993 |