| Author | Nguyen Viet Trung |
| Call Number | AIT Thesis no. TC-94-7 |
| Subject(s) | Thesis (M.Eng.) - Asian Institute of Technology, 1994
|
| Note | A thesis submitted in partial fulfillment of the requirement for the degree of Master of
Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Abstract | Error control is very essential to provide services with satisfactory performance, especially
in Asynchronous Transfer Mode (ATM) networks where a wide variety of applications of different
traffic characteristics and performance requirements are to be handled. Real time applications such
as voice, video and multimedia communications, which will be of great importance in future ATM
networks, may tolerate a certain degree of error impairments but strictly need a short time delay.
In such high bandwidth delay-product ATM networks, the latency introduced by retransmission
based error recovery schemes may be too high· for these time constrained applications, and
forward error correction becomes a more promising approach.
The research presented in this thesis consists of the design and performance evaluation of an
error correction scheme for real time traffics in ATM networks. The new scheme corrects bit
errors and recovers lost cells by applying a convolutional code to a virtual path connection.
Conventional error correction schemes for ATM real time traffics, which have been studied over
the past five years, are based on linear block coding represented by cyclic codes. In the proposed
scheme, a convolutional code, namely Berlekamp-Preparata convolutional (BPC) code combined
with an efficient cell loss detection technique using sequence number is able to correct both
random and bursty bit errors in ATM cells, especially in ATM information field, with short delay
and by simple implementation, so that· not only transmission bit errors but also lost cells due to
congestion or cell header error can be recovered. A mathematical model for decoding process of
the BPC code is developed to obtain the code performance, which is then well verified by
simulation results. Based on the BPC code performance analysis, the proposed scheme is
evaluated with proper numerical values of ATM impairments. A M/D/l queueing model is used to
assess the reduction of coding performance caused by increases of the link utilization rate due to
coding overhead and the impact of using different coding parameters. The results show
outstanding improvements in CLR and BER when the scheme is applied for a small portion (20%)
of virtual paths and the link utilization is not too high. The proposed scheme is available for virtual
channel connection as well. A possibility of BPC code for burst erasure decoding that can increase
twice the cell loss recovery capability of the proposed scheme has not yet been studied and will be
the topic for further research. |
| Year | 1994 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Other Field of Studies (No Department) |
| Academic Program/FoS | Telecommunications (TC) |
| Chairperson(s) | Takahashi, Kiyoshi
|
| Examination Committee(s) | Erke, Tapio J. ;Makelainen, Kimmo
|
| Scholarship Donor(s) | Finnish International Development Agency (FINNIDA) |
