Designing a processor core with multi-threading for ARM instruction set architecture | |
| Author | Ranawaka, R.A.D. Manesh Piyumal |
| Call Number | AIT Caps. Proj. no.EL-15-16 |
| Subject(s) | High performance processors Computer architecture |
| Note | A capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Electronics Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Caps. Proj. ; no. EL-15-16 |
| Abstract | Development a 32-bit Processor core with multithreading for ARM V2a instruction set architecture is discussed. More specifically to design pipeline hardware for a processor core with a five stage pipeline capable of handling 4 parallel threads. Designing of Thread scheduler and the Memory Management Unit would be covered under parallel research. |
| Year | 2015 |
| Corresponding Series Added Entry | Asian Institute of Technology. Caps. Proj. ; no. EL-15-16 |
| Type | Project |
| School | School of Engineering and Technology (SET) |
| Department | Bachelor Degree |
| Academic Program/FoS | Electronic Engineering (EL) |
| Chairperson(s) | Mongkol Ekpanyapong; |
| Examination Committee(s) | Chumnarn Punyasai;Krit Athikulwongse; |
| Degree | Capstone Project (B.Sc.)-Asian Institute of Technology, 2015 |