1 AIT Asian Institute of Technology

Designing rate monotonic scheduling in processor core with multi-threading for ARM architecture

AuthorTamrakar, Sujan
Call NumberAIT Caps. Proj. no.EL-15-05
Subject(s)System design Data processing
Computer architecture

NoteA capstone project report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Engineering Electronics Engineering, School of Engineeringa and Technology
PublisherAsian Institute of Technology
Series StatementCaps. Proj. ; no. EL-15-05
AbstractIn order to better utilize the resources of processor core and increase the performance efficiency of the core multithreading in a single processor can be implemented. In the main three parts of multithreading which are Hardware Pipeline, Memory Management Unit (MMU) and Scheduling algorithm, this project a Rate Monotonic Scheduling algorithm was designed for the Amber core. This design can support four threads with a static priority scheduling class for Real Time Operating Systems (RTOSs). This algorithm was also tested for compatiblitity with each stage of the pipeline modified for multithreading.
Year2015
Corresponding Series Added EntryAsian Institute of Technology. Caps. Proj. ; no. EL-15-05
TypeProject
SchoolSchool of Engineering and Technology (SET)
DepartmentBachelor Degree
Academic Program/FoSElectronic Engineering (EL)
Chairperson(s)Mongkol Ekpanyapong;
Examination Committee(s)Krit Athikulwongse;
DegreeCapstone Project (B.Sc.)-Asian Institute of Technology, 2015


Usage Metrics
View Detail0
Read PDF0
Download PDF0