| Author | Padmanabhan, Anand |
| Call Number | AIT Thesis no.ME-06-03 |
| Subject(s) | Metal oxide semiconductors, Complementary
|
| Note | A thesis submitted in partial fulfillment of the requirements for the degree of Master of Engineering, School of Engineering and Technology |
| Publisher | Asian Institute of Technology |
| Series Statement | Thesis ; no. ME-06-03 |
| Abstract | Semiconductor device functioning is commonly degraded by series resistance. The extent of performance degradation depends on the series resistance of the device, operating current flowing through the device, and on a number of other constraints. The series resistance depends on the semiconductor resistivity, on the contact resistance, and sometimes on geometrical factors. This thesis focuses on the design of a highly reliable, repeatable and reproducible low cost arrangement to electrically characterize the series resistance for 0.8 micron CMOS technology. Non-Linear Regression models developed in this study estimates the precise value of sheet resistance and junction depth for several real-time ion implant conditions and the approxiniate value of the contact resistance for a given sheet resistance. The optimum ion-implant condition for 0.8 micron CMOS technology is presented in this thesis |
| Year | 2006 |
| Corresponding Series Added Entry | Asian Institute of Technology. Thesis ; no. ME-06-03 |
| Type | Thesis |
| School | School of Engineering and Technology (SET) |
| Department | Department of Industrial Systems Engineering (DISE) |
| Academic Program/FoS | Microelectronics (ME) |
| Chairperson(s) | Lertsak Lekawat,; |
| Examination Committee(s) | Amporn Poyai;Afzulpurkar, Nitin V; |
| Scholarship Donor(s) | Asian Institute of Technology Fellowship; |
| Degree | Thesis (M.Eng.) - Asian Institute of Technology, 2006 |